The present invention relates to a mounting technology that couples, to one semiconductor component, a plurality of other semiconductor components in a fly-by mode, and for example, relates to a technology that is effective by being applied to an electronic device which is referred to as a mother board, a system board or the like, and in which a plurality of DDR3-SDRAMs (Double Data Rate3-SDRAMs) is mounted on a microcomputer in a fly-by mode over a mounting substrate.
There are the following examples of documents that describe quality improvement of signals of command/address, control system and the like, associated with memory access in an electronic device having a control device such as a microcomputer being a semiconductor component and a plurality of memory devices being a semiconductor component.
Japanese Patent Laid-Open No. 2006-237385 describes that a data system wiring is made shorter than a command/address system wiring when a microcomputer and a plurality of memory devices are mounted on a mounting substrate. The data system wiring is laid down by using a free space between the memory devices. The command/address system wiring bypasses the side of the mounting substrate. Thereby, it is possible to reduce wiring impedance of wirings of data and data strobe system and achieve shortening of the wirings.
Japanese Patent Laid-Open No. 2009-223854 describes measures to easily align a phase difference between a command/address signal and a clock signal due to a difference of signal load in the case where a microcomputer controls a plurality of DDR-SDRAMs and when a clock wiring is shared by the DDR-SDRAMs in order to reduce the crock wiring. Here, the command/address signal can be outputted earlier than the cycle start phase of the clock signal.
Japanese Patent Laid-Open No. 2012-8920 describes measures for a case where a system board in which a plurality of DIMMs (Dual Inline Memory Modules) is mounted has a T-junction structure and a fly-by structure as wiring structures in the DIMMs and the difference between the structures cannot be dealt with by only timing control such as leveling control by a memory controller. Here, capacitance element is interposed in a path that branches from a propagation path of a control system signal such as an enable signal on which the leveling control is performed and that reaches a ground plane. The capacitance element functions as a short path for a harmonic component of the control system signal, and thus the capacitance element can enhance the signal quality of the control system signal.